In AV processing systems for communicating or recording/reproducing AV data, in order to reduce the bandwidth of a communication means or the capacity of a storage medium, encoding pictures or sounds and decoding the data at the reproduction are performed. As methods for coding moving pictures as international standards, there are MPEG 1, 2, 4, and the like. These coding methods are methods comprising combinations of motion vector estimation, motion compensation, DCT (Discrete Cosine Transform), quantization, VLC (Variable Length Coding), and the like. Further, when enhancing the quality of the picture or reducing and enlarging the picture, processing such as filtering, character data processing, graphics processing, data transmission through communication lines must be carried out. In these AV processing systems, requesters perform respective processing using a common memory.
As an example of the conventional bus controller, Japanese Published Patent Application No. 2001-184300 shows a bus controller that changes priorities of arbiters (p. 5 [0026]p. 6 [0047], FIG. 1). The description of this prior art will be given with reference to FIG. 6, which is a diagram schematically illustrating the prior art. In FIG. 6, reference numeral 61 denotes a common memory, numeral 62 denotes a bus controller, numeral 63 denotes a first requester, numeral 64 denotes a second requester, and numeral 65 denotes a third requester.
A picture coding system is supposed as an example of the AV processing system. It is assumed that the first requester 63 performs filtering of pictures, the second requester 64 performs picture coding, and the third requester 65 performs data transmission via an information communication interface.
The first requester 63 and the second requester 64 perform realtime processing, and require a prescribed amount of access to a common memory or a prescribed amount of data processing in a time corresponding to a one-frame picture. On the contrary, the third requester 65 performs non-realtime processing, and performs an access to a common memory or data processing irregularly as compared to the requesters that perform the picture processing.
A structure of the bus controller 62 is shown in FIG. 5. In FIG. 5, numeral 51 denotes an arbiter, and numeral 52 denotes a protocol conversion means. When request signals from the plural requesters are inputted to the bus controller 62, the arbiter 51 supplies an enabling signal to one of the requesters in accordance with the priority. The protocol conversion means 52 has an ability of protocol converting a requester access signal (RA) indicating an address, data, and reading/writing, which is used for an access by the requester, into a common memory access signal (CMA), and a buffering ability for the protocol conversion or access speed conversion. As the common memory access signals (CMA), there are Row address and Column address outputs for accessing an SDRAM access, or a command issuance signal.
The first requester 63, the second requester 64, and the third requester 65 issue access requests for accessing the common memory 61 to the bus controller 62 in accordance with processings in the respective requesters, and access the common memory 61 through the protocol conversion by the bus controller 62 in accordance with a permission by the bus controller 62. In other words, an access of the common memory 61 is performed in accordance with the common memory access signal (CMA).
FIGS. 7(a) and 7(b) show examples of the cycle numbers. FIG. 7(a) shows the cycle numbers of the requesters. For simplicity, it is assumed that the first requester (REQ1) and the second requester (REQ2) require two accesses in a one-frame time, respectively, and the third requester (REQ3) requires zero or one access in a one-frame time, and respective requesters need an access to data that comprise a prescribed number of words. It is assumed here that the cycle number is equal to the clock number at the side of the common memory. The clock number at the side of the common memory may be changed dependent on the address which is accessed by the respective requester with respective cycle number.
In the case of SDRAM, even when data comprising the same number of words are to be accessed, in order to access the data in a minimum cycle number, address information, a command, or a sequence must be changed adaptively to the SDRAM according to whether the row address should be changed or whether the row address is a consecutive address.
As for the first requester (REQ1), the maximum cycle number is denoted by N1(max), the minimum cycle number is denoted by N1(min), and the average cycle number is denoted by N1(ave.). N1(max)−N1(ave.) is shown in black, and N1(ave.)−N1(min) is shown in white. The same applies to the second requester (REQ2).
FIG. 7(b) shows the total number of cycles in a one-frame time and designing of this cycle number. The cycle number for an access to the common memory in one frame time has a maximum value of N1(max)×2+N2(max)×2+N3(max)×1. Therefore, in order to avoid a failure of a system at the designing, it is necessary that this maximum cycle number should be ensured in one frame time. As this is the case where all accesses are made in the maximum cycle number, it is not expected that this situation occurs very frequently.
As a typical example, there are situations where the cycle number is N1(ave.)×2+N2(ave.)×2 or N1(min)+N2(max)+N1(max)+N2(min), without including the third requester (REQ3) in a one frame time. These situations are supposed to occur relatively often. Further, when all accesses are made in the minimum cycle number, only the cycle number of: N1(min)×2+N2(min)×2 is included in one frame time.
As, in the prior art, the system design is carried out in the maximum cycle number, which may not occur so frequently but has actually occurred, the cycle number per one frame time becomes large, and accordingly, the operation frequency of the common memory becomes higher, whereby the costs of the common memory and the circuit, or the difficulty in designing the system may be increased.
Further, when the cycle number in the common memory access is increased by a modification or an increase in applications after designing the system, a new bus system having a higher operation frequency is needed, thereby leading to an increase in the difficulty in designing, or increases in costs of the designing and production due to re-designing.